IEEE 2023 VLSI Projects
1.High-Density Shift-Register-Based Rapid Single-Flux-Quantum Memory System for Bit-Serial
Microprocessors
2.Area-Efficient SOT-MRAM With a Schottky Diode
3.2.31-Gb/s/ch Area-Efficient Crosstalk Canceled Hybrid Capacitive Coupling Interconnect for 3-D
Integration
4.An area-efficient partially reconfigurable crossbar switch with low reconfiguration delay
5.FTCAM: An Area-Efficient Flash-Based Ternary CAM Design
1 40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled Technique for SerDes Interface
2 A 0.25-V 28-nW 58-dB Dynamic Range Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process
3 A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4× Oversampling
4 A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes
5 A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT
6 A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding
7 A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications FIR Filter
8 A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors
9 A Low Power and High Sensing Margin Non-Volatile Full Adder Using Racetrack Memory
10 A Low-Cost Hardware Architecture for Illumination Adjustment in Real-Time Applications
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