VLSI Projects for
MTech Students —
Hardware & Software

India's most comprehensive VLSI project platform. IEEE 2026 topics across FPGA design, ASIC implementation, Low Power VLSI, SoC, Digital Design, Mixed-Signal and more — with full simulation & synthesis support.

VLSI Project Domains We Cover

From RTL design to tapeout-ready layouts — choose your specialisation and we match you to the best IEEE 2026 topic.

FPGA Design

Xilinx Vivado & Intel Quartus-based projects. Verilog / VHDL / SystemVerilog RTL implementation on Artix-7, Cyclone V.

ASIC Design & Synthesis

Full-custom and standard-cell ASIC design using Synopsys DC, Cadence Genus. Timing closure, DFT, and ECO flows.

Low Power VLSI

Clock gating, power gating, multi-Vt, DVFS techniques. UPF-based power intent with Cadence Voltus.

Physical Design (PnR)

Floorplanning, placement, CTS, routing with Cadence Innovus & Synopsys ICC2. DRC/LVS sign-off.

Mixed-Signal & Analog

ADC/DAC design, PLL, OpAmp, bandgap reference using Cadence Spectre, HSPICE on TSMC/UMC PDKs.

SoC & Embedded VLSI

RISC-V SoC, ARM Cortex-M integration, AXI/AHB bus fabric, peripheral IP design and verification.

Functional Verification

UVM-based testbench, assertion-based verification (SVA), code/functional coverage using Cadence SimVision.

AI/ML Hardware Accelerators

FPGA/ASIC-based CNN, Transformer, and inference accelerator architectures. Systolic arrays, near-memory computing.

IEEE 2026 VLSI Project Topics for MTech

All topics sourced from IEEE Xplore 2025–2026 journals (TVLSI, JSSC, TCAS-I/II, TECS). Hardware (HW), Software/Simulation (SW), Mixed (MIX) tags included.

#	Project Title	Domain	Type	Tools / Tech	Complexity
01	Low-Latency AES-256 Encryption Engine on FPGA with Pipeline Folding	FPGA Design	HW	Vivado · Verilog	⭐⭐⭐
02	Reconfigurable FIR Filter Bank for Software-Defined Radio on Artix-7	FPGA / DSP	HW	Vivado · MATLAB	⭐⭐⭐
03	FPGA-Based Real-Time Edge Detection Using Sobel Operator with HLS	FPGA / HLS	MIX	Vitis HLS · OpenCV	⭐⭐
04	Multi-Core RISC-V Processor with Out-of-Order Execution on Cyclone V	FPGA / Arch	HW	Quartus · SystemVerilog	⭐⭐⭐⭐⭐
05	Scalable NoC Router Architecture for Manycore FPGA Systems	FPGA / NoC	HW	Vivado · Verilog	⭐⭐⭐⭐
06	Ultra-Low-Power 32-bit RISC-V Core ASIC Synthesis at 7 nm Node	ASIC Design	HW	Synopsys DC · TSMC 7nm	⭐⭐⭐⭐⭐
07	High-Speed SHA-3 Cryptographic Hash ASIC with DFT Insertion	ASIC / Security	HW	Genus · Innovus	⭐⭐⭐⭐
08	ASIC Implementation of Polar Code Decoder for 5G NR Standard	ASIC / Comm	HW	DC · ICC2 · UMC 28nm	⭐⭐⭐⭐
09	Design and Verification of PCIe Gen 5 PHY Layer Controller	ASIC / Interface	MIX	Synopsys · UVM	⭐⭐⭐⭐⭐
10	Sub-Threshold SRAM Design with Adaptive Body Biasing for IoT SoCs	Low Power VLSI	HW	Cadence Spectre · 22nm	⭐⭐⭐⭐
11	Power-Gating Strategy for Always-On Domain in Wearable SoC at 28 nm	Low Power VLSI	SW	Voltus · UPF	⭐⭐⭐
12	Multi-Vt Cell Optimization for Leakage Reduction in 16nm FinFET	Low Power VLSI	SW	Synopsys DC · PrimeTime	⭐⭐⭐⭐
13	Dynamic Voltage and Frequency Scaling Controller for ML Accelerator	Low Power / AI	MIX	Vivado · Python	⭐⭐⭐
14	Automated Floorplanning of Heterogeneous SoC Using Simulated Annealing	Physical Design	SW	Cadence Innovus · TCL	⭐⭐⭐⭐
15	Clock Tree Synthesis Optimization for Skew Minimization at 7 nm	Physical Design	SW	Innovus · Tempus	⭐⭐⭐⭐
16	DRC-Clean Full Chip PnR of H.264 Encoder Core at 28 nm	Physical Design	MIX	ICC2 · Calibre	⭐⭐⭐⭐⭐
17	12-bit 200 MSPS SAR ADC Design in 180 nm CMOS for Medical IoT	Mixed-Signal	HW	Cadence Spectre · TSMC 180nm	⭐⭐⭐⭐
18	Low-Jitter Fractional-N PLL for 5G mmWave Applications	Mixed-Signal / RF	HW	Spectre · ADS	⭐⭐⭐⭐⭐
19	Sigma-Delta Modulator for High-Resolution Audio ADC in 65 nm	Mixed-Signal	HW	HSPICE · MATLAB	⭐⭐⭐⭐
20	Bandgap Reference with Curvature Correction for Wide-Temperature SoC	Analog / Mixed	HW	Cadence Virtuoso	⭐⭐⭐
21	Systolic Array CNN Accelerator for Real-Time Object Detection on FPGA	AI Hardware	MIX	Vitis AI · Vivado	⭐⭐⭐⭐⭐
22	ASIC Design of Transformer Self-Attention Accelerator at 22 nm	AI Hardware	HW	Synopsys DC · 22nm PDK	⭐⭐⭐⭐⭐
23	Binary Neural Network Hardware Accelerator with Bit-Serial Arithmetic	AI Hardware	HW	Quartus · SystemVerilog	⭐⭐⭐⭐
24	Processing-in-Memory Architecture for Sparse Matrix DNN Workloads	AI / Memory	SW	Gem5 · CACTI	⭐⭐⭐⭐
25	UVM-Based Verification of AXI4 Interconnect with Functional Coverage	Verification	SW	Xcelium · UVM	⭐⭐⭐
26	Formal Verification of RISC-V Instruction Fetch Unit Using JasperGold	Formal Verification	SW	JasperGold · SVA	⭐⭐⭐⭐
27	Emulation-Accelerated Verification of USB 3.2 Host Controller	Verification	MIX	Palladium · SystemVerilog	⭐⭐⭐⭐⭐
28	RISC-V SoC with On-Chip UART, SPI, I2C Peripherals on FPGA	SoC / Embedded	MIX	Vivado · FreeRTOS	⭐⭐⭐
29	Hardware Root of Trust for Secure Boot in IoT SoC Design	SoC / Security	HW	Quartus · ARM TZ	⭐⭐⭐⭐
30	Chiplet-Based Heterogeneous Integration with UCIe 2.0 Die-to-Die Interface	SoC / Packaging	MIX	Synopsys 3DIC · UCIe	⭐⭐⭐⭐⭐
31	Neuromorphic Spiking Neural Network Hardware for Edge Inference	Neuromorphic	HW	Vivado · NEST Sim	⭐⭐⭐⭐⭐
32	Post-Quantum Lattice Cryptography Accelerator (CRYSTALS-Kyber) on FPGA	Security VLSI	HW	Vivado · SystemVerilog	⭐⭐⭐⭐
33	FinFET-Based 6T SRAM Stability Analysis with Process Variation at 7nm	Memory Design	SW	HSPICE · Monte Carlo	⭐⭐⭐⭐
34	LDPC Decoder ASIC for Wi-Fi 7 (IEEE 802.11be) Physical Layer	ASIC / Wireless	HW	Synopsys DC · TSMC 12nm	⭐⭐⭐⭐
35	Timing-Speculative Design with Error Detection for Near-Threshold Computing	Reliability VLSI	MIX	Cadence · PrimeTime	⭐⭐⭐⭐

How We Deliver Your VLSI Project

End-to-end support — from topic selection to final viva preparation.

Topic Selection

We analyse your university guidelines and suggest IEEE 2026 topics matched to your specialisation and available tools.

Literature Survey

Curated IEEE paper package with review summary, gap analysis, and scope definition for your chosen topic.

Design & Coding

RTL/schematic design, Verilog/VHDL/SystemVerilog coding with inline comments and proper documentation.

Simulation

Functional simulation, waveform verification, and timing analysis. Clean simulation results with annotated screenshots.

Synthesis & Implementation

Logical synthesis, place-and-route, timing closure, power analysis with utilisation and slack reports.

Report & Viva Prep

IEEE-format thesis, PPT, and a 1-on-1 viva session covering all technical questions panel may ask.

Frequently Asked Questions

Which universities and VLSI specialisations do you support?

We support MTech (VLSI Design), MTech (Embedded Systems), MTech (Digital Electronics), and ME (Applied Electronics) students from Anna University, VTU, JNTU, Pune University, Mumbai University, CUSAT, NIT, and all affiliated colleges across India.

Do you provide source code and simulation files?

Yes. Every project includes full RTL source code (Verilog/VHDL/SV), simulation testbenches, synthesis scripts, waveform screenshots, netlist reports, and power/area/timing analysis results — all editable and well-commented.

Can you help with both hardware and software VLSI projects?

Absolutely. We cover hardware implementation (FPGA prototyping, ASIC tape-in, layout) as well as simulation-only (EDA tool-based software projects using Cadence, Synopsys, Mentor, Xilinx). Both are equally supported.

How long does a VLSI project take to complete?

Standard projects are delivered in 10–15 working days. Complex SoC or mixed-signal projects may take 20–25 days. Express delivery in 5–7 days is available for select topics.

Are the topics based on IEEE 2025–2026 papers?

Yes. All project topics listed are sourced from IEEE Xplore journals published in 2025–2026, including IEEE TVLSI, JSSC, TCAS-I, TCAS-II, and TECS. Full reference list provided with each project.

Do you support FPGA hardware boards as deliverables?

Yes. We support Basys 3, Nexys A7, ZedBoard, Arty-A7, DE0-Nano, and DE10-Standard boards. Hardware implementation with on-board demo video is available as an add-on service.