A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding
Abstract: Sample adaptive offset (SAO) is a newly introduced in-loop filtering component in H.265/High Efficiency Video Coding (HEVC). While SAO contributes to a notable coding efficiency improvement, the estimation of SAO parameters dominates the complexity of in-loop filtering in HEVC encoding. This paper presents an efficient VLSI design for SAO estimation. Our design features a dual-clock architecture that processes statistics collection (SC) and parameter decision (PD), the two main functional blocks of SAO estimation, at high- and low-speed clocks, respectively. Such a strategy reduces the overall area by 56% by addressing the heterogeneous data flows of SC and PD. To further improve the area and power efficiency, algorithm-architecture co-optimizations are applied, including a coarse range selection (CRS) and an accumulator bit width reduction (ABR). CRS shrinks the range of fine processed bands for the band offset estimation. ABR further reduces the area by narrowing the accumulators of SC. They together achieve another 25% area reduction. The proposed VLSI design is capable of processing 8k at 120-frames/s encoding. It occupies 51k logic gates, only one-third of the circuit area of the state-of-the-art implementations.
VLSI Projects,IEEE VLSI Projects,latest vlsi projects,2018 VLSI Projects,VLSI Projects in Bangalore,VLSI projects institutes in bangalore,VLSI live projects in bangalore,VLSI academic projects,VLSI project centres,M.Tech VLSI projects in bangalore,M Tech VLSI projects institutes in bangalore,FPGA projects in bangalore,ieee vlsi,vlsi ieee papers,mtech vlsi,fpga projects using vhdl,mini project on image processing,vlsi paper,vlsi ieee papers,ieee project papers,vlsi institutes in bangalore,ofdm projects,vlsi projects using vhdl,projects based on digital signal processing,vhdl based projects,latest vlsi projects,vlsi project institutes in bangalore,VLSI Project,vlsiproject,vlsi project institute in bangalore,vlsi project idea,idea in vlsiproject,idea in vlsiprojects,idea in vlsi project,idea in vlsiprojects,M.Tech VLSI Projects in Bangalore,M.Tech FPGA Projects in Bangalore,ECE VLSI Projects in Bangalore,VLSI Academic Projects in Bangalore,VLSI Live Projects in Bangalore,VLSI Real Time Projects in Bangalore,VLSI Projects for MTech 2018,VLSI Projects for MTech 2018,VLSI Projects for MTech in Bangalore,FPGA based Projects for M.Tech,download 2018 VLSI Project list,VLSI project centre,VLSI academic projects,vlsi ieee papers,new vlsi projects,mtech vlsi,fpga projects using vhdl,mini project on image processing,vlsi paper,vlsi ieee papers,ieee project papers,vlsi institutes in bangalore,ofdm projects,vlsi projects using vhdl,projects based on digital signal processing,vhdl based projects,latest vlsi projects,vlsi project institute in bangalore,vlsi project idea,idea in vlsiproject,idea in vlsiprojects,idea in vlsi project,idea in vlsiprojects
del.icio.us
Google