IEEE 2024 VLSI Projects
1.High-Density Shift-Register-Based Rapid Single-Flux-Quantum Memory System for Bit-Serial
Microprocessors
2.Area-Efficient SOT-MRAM With a Schottky Diode
3.2.31-Gb/s/ch Area-Efficient Crosstalk Canceled Hybrid Capacitive Coupling Interconnect for 3-D
Integration
4.An area-efficient partially reconfigurable crossbar switch with low reconfiguration delay
5.FTCAM: An Area-Efficient Flash-Based Ternary CAM Design
1.A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging
2.Adaptive Multi-bit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication
3.Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture
4.Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding
5.A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption
6.Resource-Efficient SRAM-based Ternary Content Addressable Memory
7.Write-Amount-Aware Management Policies for STT-RAM Caches
8.Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA
9.High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder
10.High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations
11.Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST
12.Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map
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