Drain Current Saturation in Line Tunneling-Based TFETs: An Analog Design Perspective
Abstract: This paper highlights the output current saturation in a line tunneling-based tunnel FET (LT-TFET). Thereafter, a novel method to extract the onset of saturation voltage (VDSAT) for LT-TFET is proposed for the first time. A soft saturation state is attained when the electron density in the epitaxial layer over the source region saturates with the drain bias (VDS) and the conduction band energy (EC) gets pinned. In addition, at the onset of deep saturation, the electron density in the epitaxial layer over the channel region drops below its doping level and EC becomes invariant for any further increase in VDS. The difference between gate-drain bias (VGD) is found to be a constant at the onset of saturation and remains independent of the gate-source overlap lengths (LOV). A shift in VDSAT and VGD is also observed with change in the thickness and doping of the epitaxial layer. The transconductance and output resistance are reasonably good in the soft saturation regime. Furthermore, a nominal change of ~5% in the voltage gain (AV) of a common source amplifier is observed when the n-device is biased in the either soft or deep saturation regime, without any tradeoff in the bandwidth.
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