A Dual-Data Line Read Scheme for High-Speed Low-Energy Resistive Nonvolatile Memories
Abstract: Resistance-based memory devices are considered as a strong candidate for next-generation nonvolatile memories as well as potential application in high density embedded cache. These devices can be programmed to different resistance states by applying electrical bias. Read operation then senses the programmed state by discharging a shared data line through the memory cell. However, as the dimensions of the device scale down, its resistance increases and the distribution widens, which leads to reduced sensing margins and degradation in read performance. In the proposed dual-data line (DDL) read scheme, we recycle current flowing through the memory cell during the read operation to create an additional voltage swing on a secondary data line, and combine it with the signal on the original data line to reduce sensing time and energy. Performance comparison with the conventional read scheme is derived theoretically by using circuit analysis and verified through simulation on an array critical path constructed in 65-nm technology. Results show that the DDL scheme can improve sensing margins by an average of 86%, which translates to a sensing time reduction of 47%, across various device conditions. For the same read performance, the sensing energy is decreased by 48%
VLSI Projects,IEEE VLSI Projects,latest vlsi projects,2018 VLSI Projects,VLSI Projects in Bangalore,VLSI projects institutes in bangalore,VLSI live projects in bangalore,VLSI academic projects,VLSI project centres,M.Tech VLSI projects in bangalore,M Tech VLSI projects institutes in bangalore,FPGA projects in bangalore,ieee vlsi,vlsi ieee papers,mtech vlsi,fpga projects using vhdl,mini project on image processing,vlsi paper,vlsi ieee papers,ieee project papers,vlsi institutes in bangalore,ofdm projects,vlsi projects using vhdl,projects based on digital signal processing,vhdl based projects,latest vlsi projects,vlsi project institutes in bangalore,VLSI Project,vlsiproject,vlsi project institute in bangalore,vlsi project idea,idea in vlsiproject,idea in vlsiprojects,idea in vlsi project,idea in vlsiprojects,M.Tech VLSI Projects in Bangalore,M.Tech FPGA Projects in Bangalore,ECE VLSI Projects in Bangalore,VLSI Academic Projects in Bangalore,VLSI Live Projects in Bangalore,VLSI Real Time Projects in Bangalore,VLSI Projects for MTech 2018,VLSI Projects for MTech 2018,VLSI Projects for MTech in Bangalore,FPGA based Projects for M.Tech,download 2018 VLSI Project list,VLSI project centre,VLSI academic projects,vlsi ieee papers,new vlsi projects,mtech vlsi,fpga projects using vhdl,mini project on image processing,vlsi paper,vlsi ieee papers,ieee project papers,vlsi institutes in bangalore,ofdm projects,vlsi projects using vhdl,projects based on digital signal processing,vhdl based projects,latest vlsi projects,vlsi project institute in bangalore,vlsi project idea,idea in vlsiproject,idea in vlsiprojects,idea in vlsi project,idea in vlsiprojects
del.icio.us
Google